The present invention pertains to a shift register; in particular, to a bidirectional shift register.
Conventionally, a gate driver utilizing a shift register has been utilized for a panel display device utilizing liquid crystal and plasma.
Symbol 200 in FIG. 8 indicates a panel type display device provided with panel 211, multiple pixels 210 formed on panel 211, gate driver 102, and source driver 202.
Multiple (N, in this case) gate lines 2211-221N and multiple (M, in this case) source lines 2211-222M are connected to gate driver 102 and source driver 202, respectively.
Pixels 210 are arranged in the form of a matrix, and a transistor is provided in each pixel 210. In the transistor in 1 pixel 210, a gate terminal and a source terminal are connected to gate line 221x and source line 222m corresponding to its position (n,m) in the matrix.
Drain terminal of the transistor in each pixel is connected to an electrode used to apply a voltage to a displaying member, such as a liquid crystal or a light-emitting element, wherein the displaying member in pixel 210 becomes bright or dark as the transistor in pixel 210 becomes conductive according to the voltage applied to the source terminal of said transistor.
In said display device 200, gate driver 102 supplies a signal to the respective gate lines in order to make the transistors in the respective pixels conductive in a time-divided manner.
The order the signal is supplied can be either in the forward direction, that is, from first gate line 2211 toward the Nth gate line 221N, or in the backward direction. When the signal is supplied from gate driver 102 to gate line 221n, the signal which makes the transistors conductive is applied at once to the gate terminals of M pixels 210n,1-210n,M connected to said gate line 221n, and the electrical connection is achieved between the drain terminals and the source terminals of M pixels 210n,1-210n,M connected to said gate line 221n.
When the signal is applied to gate line 221n, source driver 202 applies a voltage corresponding to the display condition of M pixels 210n,1-210n,M connected to said gate line 221n.
Therefore, M pixels 210n,1-210n,M connected to gate line 221n become bright or dark according to the level of the voltage supplied by source driver 202.
When the display of 1 gate line 221n is finished, a voltage is supplied to next gate line 221n+1 using the same procedure.
One screen is displayed as the first through the Nth gate lines 2211-221N are scanned in said manner.
A block diagram of a conventional internal circuit of such a gate driver 102 is shown in FIG. 6.
Said gate driver 102 has input level conversion circuit 112, shift register 105, and output level conversion circuit 106.
Output level conversion circuit 106 has multiple (N, in this case), that is, the first through the Nth, buffer circuits 1161-116N according to the quantity N of gate lines 2211-221N, wherein the output terminals of buffer circuits 1161-116N are respectively connected to gate lines 2211-221N.
Shift register 105 has multiple (N, in this case), that is, the first through the Nth, memory circuits 1151-115N according to the quantity of buffer circuits 1161-116N, wherein the output terminals of memory circuits 1151-115N are respectively connected to the input terminals of buffer circuits 1161-116N. Signals output from respective memory circuits 1151-115N are applied with voltage conversion and supplied to gate lines 2211-221N by buffer circuits 1161-116N.
Because respective memory circuits 1151-115N of said gate driver 102 have the same configuration, the detailed internal circuit of nth memory circuit 115n is shown in FIG. 7 to represent them.
Each memory circuit 1151-115N has forward transmission input terminal F, backward transmission input terminal B, and output terminal SR.
When the forward transmission input terminal and the backward transmission input terminal of nth memory circuit 115n are expressed as Fn and Bn with the suffix n, and the output terminal is expressed as SRn, output terminal SRnxe2x88x921 of (nxe2x88x921)th memory circuit 115nxe2x88x921 of the former stage is connected to forward transmission input terminal Fn of nth memory circuit 115n, output terminal SRn+1 of (n+1)th memory circuit 115n+1 of the latter stage is connected to backward transmission input terminal Bn, to which signals output from memory circuits 115nxe2x88x921 and 115n+1 of the former and the latter stages are respectively input.
Then, output terminal SRn of nth memory circuit 115n is connected to forward input terminal Fn+1 of memory circuit 115n+1 of the latter stage and backward transmission input terminal Bnxe2x88x921 of memory circuit 115nxe2x88x921 of the former stage.
Selection circuit 117, first and second gate circuits 124 and 125, and first and second latch circuits 118 and 119 are provided inside of respective memory circuits 1151-115N.
Selection circuit 117 is connected to forward transmission input terminal Fn and backward transmission input terminal Bn. In addition, selection signal LR and inverted selection signal XLR with the opposite polarity are input to selection circuit 117 from input level conversion circuit 112, whereby either forward transmission input terminal Fn or backward transmission input terminal Bn is selected, depending on the logical combination of highs and lows of selection signal LR and inverted selection signal XLR, and the selected input terminal gets connected to first gate circuit 124 of the latter stage via inverter 123.
Clock signal CK and inverted clock signal XCK with the opposite polarity are input to first and second gate circuits 124 and 125. First gate circuit 124 is shut off when clock signal CK is high and becomes conductive as it changes from high to low in order to transmit the signal to first latch circuit 118 of the latter stage.
First latch circuit 118 holds the signal input and outputs said signal to second latch circuit 119 of the latter stage via second gate circuit 125.
Second gate circuit 125 becomes conductive when clock signal CK is high, and it is shut off while first gate circuit 124 is conductive.
Therefore, as soon as clock signal CK changes from low to high, and first gate circuit 124 changes from the conductive state to the shut-off state, second gate circuit 125 becomes conductive, and the output of first latch circuit 118 is input to second latch circuit 119. As a result of said operation, a signal with the same logic as that of the high or the low signal held in first latch circuit 118 gets held in second latch circuit 119. The signal held in second latch circuit 119 is output from output terminal SRn.
When clock signal CK changes from high to low as described above, the signal input from forward transmission input terminal Fn or backward transmission input terminal Bn is latched into first latch circuit 118. Then, when clock signal CK changes from low to high, the signal latched into first latch circuit 118 is transferred to second latch circuit 119 for output.
Therefore, when forward transmission input terminal Fn is selected, the signals stored in respective memory circuits 1151-115Nxe2x88x921 are transmitted to memory circuits 1152-115N of the latter stage as 1 cycle of clock signal CK is completed. When the backward transmission input terminal is selected, the signals stored in respective memory circuits 1152-115N are transmitted to memory circuits 1151-115Nxe2x88x921 of the former stage as 1 cycle of clock signal CK is completed.
FIG. 9 is a timing chart for explaining the signal transmitting condition when forward transmission input terminal Fn is selected, wherein symbol t0 indicates the time high pulse signal STV is input into memory circuit 1151 of the initial stage.
At said time t0, clock signal CK, which has changed from high to low, is input to memory circuit 1151 of the initial stage along with pulse signal STV, first gate circuit 124 in memory circuit 1151 of the initial stage becomes conductive due to said clock signal CK, and the same high signal as pulse signal STV gets held by first latch circuit 118.
Next, when clock signal CK changes from low to high at time t1, second gate circuit 125 becomes conductive, and the high signal held in first latch circuit 118 is transferred to second latch circuit 119 and output to buffer circuit 1161 of the initial stage and memory circuit 1152 of the next stage from output terminal SR1.
At memory circuit 1152 of the next stage, the high signal is output from output terminal SR2 at time t2 as 1 cycle of clock signal CK is completed after time t1.
High signal is output from output terminal SRn of nth memory circuit 115n at time tn in the manner described above.
Although shift register 105 of the prior art has the aforementioned configuration, as the display device becomes much smaller but more precise, the gate driver is provided with more pins, so that the number of the elements in the circuit ends up increasing.
In addition, because the power consumption increases as the number of circuits increases, this problem must be solved before it can be used in portable equipment.
The present invention was created in order to solve the aforementioned inconvenience of the prior art, and its purpose is to present a shift register by which a low-power-consumption gate circuit can be configured.
In accordance with one aspect of the present invention the shift register is provided with a first memory circuit having a first selection circuit which outputs a signal to be input to a first input terminal or a second input terminal selectively according to a selection signal, a first gate circuit which outputs the signal output from the aforementioned first selection circuit selectively according to a first clock signal, and a first latch circuit which holds the signal output from the aforementioned first gate circuit and outputs the signal to a first output terminal and a second memory circuit having a second selection circuit which outputs a signal to be input to a third input terminal or a fourth input terminal connected the aforementioned first output terminal selectively according to the aforementioned selection signal, a second gate circuit which outputs the signal output from the aforementioned second selection circuit selectively according to a second clock signal complementary to the aforementioned first clock signal, and a second latch circuit which holds the signal output from the aforementioned second gate circuit and outputs the signal to a second output terminal; and memory circuits having the same configurations as those of the aforementioned first and second memory circuits are connected alternately in series.
In addition, in accordance with a second aspect of the present invention, it is desirable that the aforementioned first memory circuit has a first logic circuit which applies a logical operation to the signal output from the aforementioned first latch circuit and the aforementioned first clock signal and outputs the resulting logical operation signal to a third output terminal, and the aforementioned second memory circuit has a second logic circuit which applies a logical operation to the signal output from the aforementioned second latch circuit and the aforementioned second clock signal and outputs the resulting logical operation signal to a fourth output terminal.
Furthermore, in accordance with another aspect of the invention, it is desirable that the aforementioned first input terminal is connected to the second output terminal of the memory circuit of the former stage, the aforementioned first output terminal is connected to the fourth input terminal of the memory circuit of the former stage, the aforementioned fourth input terminal is connected to the first output terminal of the memory circuit of the latter stage, and the aforementioned second output terminal is connected to the aforementioned second input terminal and the first input terminal of the memory circuit of the latter stage.
One aspect of the present invention is configured in the aforementioned manner, wherein when the data signals are output from the output terminals of the memory circuits in the odd-numbered locations as the gate circuits of the memory circuits in the odd-numbered locations become conductive, the gate circuits of the memory circuits in the even-numbered locations are shut off. Next, when the gate circuits of the memory circuits in the odd-numbered locations are shut off, the gate circuits of the memory circuits in the even-numbered locations become conductive, and the data signals output from the memory circuits in the odd-numbered locations are input to the latch circuits of the memory circuits in the even-numbered locations.
As described above, the gate circuits of the memory circuits in the odd-numbered locations and the gate circuits of the memory circuits in the even-numbered locations operate complementary to each other, and the respective memory circuits output the data signals input from the memory circuits of the former stage to the memory circuits of the latter stage according to the (first or second) clock signal.
In addition, in a further aspect of the present invention, the direction the data signals are shifted can be reversed by changing the logic of the selection signal input to the selection circuit of each memory circuit.